The embodiments described herein relate to processor design and architecture. More specifically, the embodiments relate to partitioning the processor design for architecturally defined timing domains that influence design cycle time and pipeline depth.
Timing design of a processor is static in that design cycle time is applied uniformly across all circuits within a time domain based on an assumption of equal use. The design cycle time may be determined based on an expected workload of the processor. In one embodiment, the design cycle time is determined based on a thermal design point (TDP) for the processor. As is known in the art, the TDP of a processor is a maximum amount of heat generated by the processor during typical operation. However, many workloads do not approach the TDP of the processor, and as such these workloads may benefit from a faster cycle time.
One known solution for addressing the workload differentiation is accomplished using a critical path monitor (CPM), which is a circuit that measures an available timing margin in real-time, coupling output from the circuit to a clock generation circuit to adjust clock frequency within cycles in response to an excess or inadequate timing margin. The CPM periodically adjusts a processor voltage or frequency. However, the CPM continues to employ a uniform design cycle.